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Semiconductor silicon wafers are the foundation of the integrated circuit industry. More than 90% of LSI and VLSI devices are fabricated on high-purity polished and epitaxial silicon wafers.

Founded in 2000, QL has focused on semiconductor wafer manufacturing for 26 years, and was the first company in mainland China to integrate the complete wafer flow — crystal growth, lapping, polishing and epitaxy. QL supplies silicon ingots, lapped wafers, polished wafers and epitaxial wafers in 150 / 200 / 300 mm diameters.

Through our research collaboration with the State Key Laboratory of Silicon and Advanced Semiconductor Materials at Zhejiang University, we deliver silicon material solutions for power devices, logic and analog ICs, memory, CMOS image sensors (CIS) and MEMS — from R&D samples to automotive-grade volume production.

26 years in wafer manufacturing Full in-house process control 150 / 200 / 300 mm <100> / <111> substrate orientations Zhejiang University platform

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Product Categories
Browse by process family. To select material by device, see “Solutions by Device” in each category.
QL epitaxial wafers are available in 150, 200 and 300 mm diameters and in <100> and <111> substrate orientations. Epitaxial thickness ranges from 1 to 180 μm and resistivity from 0.005 to 1200 Ω·cm. Three dopant sources are available: phosphine (PH3), arsine (AsH3) and diborane (B2H6). Substrate and epi-layer combinations are freely selectable, and multilayer can be customized

Specifications

Diameter150, 200 and 300 mm
Substrate typeheavily doped P+ (B), heavily doped N+ (Ph / As / Sb), lightly doped P− (B), lightly doped N− (Ph), buried layer
Substrate orientation<100>, <111>
Substrate resistivity
(heavily doped)
P-type B: 1–5 mΩ·cm | 10–20 mΩ·cm
N-type Ph: 0.8–1.85 mΩ·cm
N-type As: 1.8–5 mΩ·cm
N-type Sb: 8–20 mΩ·cm
Substrate resistivity
(lightly doped)
P-type B: 8–12 Ω·cm | 1–100 Ω·cm
N-type Ph: 7–16 Ω·cm | 1–100 Ω·cm
Custom development: > 5000 Ω·cm, > 10000 Ω·cm …
Epitaxial dopant sourceN-type phosphine PH3 | N-type arsine AsH3 | P-type diborane B2H6
Epitaxial thickness
and resistivity
N-type PH3: THK 1–180 μm | RES 0.005–1200 Ω·cm
N-type AsH3: THK 1–180 μm | RES 0.005–150 Ω·cmNo.1 Leading company for AsH3 Epi Mass Production
P-type B2H6: THK 1–60 μm | RES 0.005–800 Ω·cm
Epitaxial structurefree choice of substrate and epi-layer combinations; free choice of multilayer epi stacks

Solutions by Device7 device families

Device familyKey technologiesExample structures
MOSFET
incl. SGT-MOS, SJ-MOS, FR-MOS, LDMOS and other structures
covers 12–1500 V
ultra-low-resistivity CZ silicon crystal growth; AsH3 buffer-layer epitaxy; misfit-free epitaxy; multilayer epitaxial structure control; thick-layer epitaxial growth defect control N/N+, N/N/N+, N/N/N/N+, P/P+, P/P/P+
SBD / TMBS
covers 20–250 V
epitaxial autodoping control; PN junction profile control N/N+, N/N/N+, N/N/N/N+
FRD
platinum diffusion / irradiation; covers 350–1700 V
thick-layer epitaxial growth defect control; thick-layer epitaxial slip defect control; epitaxial autodoping elimination N/N+, N/N/N+, N/N/N/N+
IGBT
covers 650–1350 V
thick-layer epitaxial growth defect control; high-flatness thick-layer epitaxial wafer; epitaxial autodoping elimination N/N, N/N/N
TVS
incl. bidirectional / low-capacitance types; covers 3.3–24 V
epitaxial SRP transition region control; PN junction profile control P/P+, N/P+, N/P/N+, P/P/P/N+, N/N+
CIS (CMOS image sensor) BMD internal gettering (IG); full-process metal control; graded epitaxy P/P+
Analog & Digital IC
BCD / Logic
high-flatness control via a hybrid substrate + epitaxy process; crystal defect characterization P/P, P/P+, N/P

Core Technologies

① Ultra-low-resistivity CZ silicon crystal growth

QL grows ultra-low-resistivity, heavily doped crystals by the Czochralski (CZ) method, steadily lowering the resistivity of heavily doped substrates: 200 mm substrates reach Ph < 0.9 / As < 2.0 / B < 1.1 mΩ·cm, and 300 mm substrates Ph < 1.1 / As < 2.2 / B < 1.5 mΩ·cm.

Customer benefit: lower substrate resistivity directly reduces device on-resistance — RDS(on) drops by 10–20%.

② Ultra-low-resistivity substrate epitaxial stacking-fault elimination

On ultra-low-resistivity (< 0.9 mΩ·cm) phosphorus (Ph) substrate wafers, this technology suppresses stacking-fault formation at the epi surface.

Customer benefit: lowers device leakage and improves yield and wafer-to-wafer consistency.

③ AsH3 buffer-layer epitaxy

Arsine serves as the buffer-layer dopant source. Arsenic’s lattice constant closely matches that of silicon, so lattice mismatch stays small and epitaxial defect density is lower. Arsenic also has high solid solubility in silicon (around 10¹⁹ cm⁻³), which allows buffer-layer resistivity as low as 0.005 Ω·cm. Its diffusion coefficient is an order of magnitude lower than that of phosphorus, limiting impurity diffusion during high-temperature processing.

Customer benefit: reduces epitaxial defect density while limiting impurity diffusion during high-temperature processing.

④ Misfit-free epitaxy

Misfit dislocations in P−/P+ epi wafers come from the lattice-constant difference between the epi layer and the substrate. They are most severe with ultra-low-resistivity substrates and thick epi layers, and they raise device leakage and lower breakdown voltage. Misfit-Free Epi uses growth-process control to deliver a misfit-dislocation-free epi surface.

Customer benefit: reduces device leakage and improves breakdown characteristics and yield consistency.

⑤ Epitaxial autodoping control

During high-temperature epitaxy, dopants in the heavily doped substrate diffuse toward the wafer edge, which lowers edge resistivity and degrades within-wafer uniformity. Autodoping control limits that diffusion.

Customer benefit: raises edge breakdown voltage (BV) and tightens within-wafer BV spread.

⑥ Thick-layer epitaxial slip defect control

Slip defects on thick epi surfaces form leakage paths. Process control delivers low-slip or slip-free surfaces.

Customer benefit: significantly reduces device leakage current.

⑦ High-flatness thick-layer epitaxy

For high-voltage MOSFET epitaxy ≥ 50 μm thick, this technology delivers a defect-free backside, crown-free edges and high local flatness.

Customer benefit: reduces lithography defocus risk and widens the lithography process window, improving device yield.

⑧ BMD internal gettering and full-process metal control

Stabilizes BMD (internal gettering) density and size during crystal growth and defect engineering, and extends metal control across the full flow: crystal hot zone → substrate processing → epitaxial growth.

Customer benefit: for CIS, delivers strong white-spot and dark-current performance along with device-to-device consistency.

Applications

  • Discrete devices: MOSFET (incl. SGT-MOS, SJ-MOS, FR-MOS, LDMOS and other structures), IGBT, FRD, SBD, TMBS, TVS, etc.
  • Digital / analog ICs: Logic IC, MCU, BCD, etc.
  • Image sensors: FSI CIS, BSI CIS, etc.
  • Optoelectronic devices: photodiodes (PD), phototransistors (PT), etc.
QL polished wafers are available in 150, 200 and 300 mm diameters and in <100>, <111> and <110> orientations. They come in two grades: lightly doped polished wafers for digital / analog ICs, memory devices and test wafers, and heavily doped (For Epi) polished wafers used as epitaxial substrates. Surface finishes include single-side polishing and double-side polishing (DSP), and a range of P-type and N-type dopants is supported.

Specifications — Lightly Doped150 / 200 / 300 mm

Conductive type · dopantResistivityMain use
P-type · boron B8–12 Ω·cm | 1–100 Ω·cmdigital / analog ICs, memory devices, test wafers
N-type · phosphorus Ph7–16 Ω·cm | 1–100 Ω·cmdigital / analog ICs, memory devices, IGBT, MEMS, test wafers
Custom development> 5000 Ω·cm | > 10000 Ω·cmcustom applications for high-resistivity / ultra-high-resistivity RF devices

Specifications — Heavily DopedFor Epi

Conductive type · dopantResistivityMain use
P-type · boron B1–5 mΩ·cm | 10–20 mΩ·cmepitaxial substrate
N-type · phosphorus Ph0.8–1.85 mΩ·cmepitaxial substrate
N-type · arsenic As1.8–5 mΩ·cmepitaxial substrate
N-type · antimony Sb8–20 mΩ·cmepitaxial substrate

Solutions by Device5 substrate applications

Substrate applicationKey technologiesExample products
Power discrete
MOSFET / SGT / SJ / FRD / SBD / TMBS / TVS
ultra-low-resistivity CZ silicon crystal growth heavily doped phosphorus ≤ 0.9 mΩ·cm substrates, heavily doped arsenic ≤ 2.0 mΩ·cm substrates (150 / 200 / 300 mm)
IGBT (MCZ) MCZ ultra-low oxygen control; low-COP perfect crystal growth 8-inch lightly doped phosphorus MCZ platform at 30 / 45 / 60 / 90 Ω·cm
Analog & Digital IC
BCD / HVIC / Logic / Analog / LED Driver
vacancy-type COP-free crystal growth; crystal defect characterization; high-flatness control; BMD internal gettering 8 / 12-inch P-type lightly doped 8–12, 15–25 Ω·cm
Memory
DRAM / Flash
perfect crystal growth 12-inch P-type lightly doped 8–12 Ω·cm
MEMS ultra-high-resistivity crystal pulling; surface poly micro-polishing / Trap-Rich; MEMS warp/bow control 8-inch N08 1.5–3 Ω·cm, P08 > 10000 Ω·cm

Core Technologies

① Ultra-low-resistivity CZ silicon crystal growth

QL grows ultra-low-resistivity, heavily doped crystals by the Czochralski (CZ) method, lowering the resistivity of heavily doped substrates: 200 mm substrates reach Ph < 0.9 / As < 2.0 / B < 1.1 mΩ·cm, and 300 mm substrates Ph < 1.1 / As < 2.2 / B < 1.5 mΩ·cm.

Customer benefit: as a power-device epitaxial substrate, lower substrate resistivity reduces RDS(on) by 10–20%.

② MCZ ultra-low oxygen control (dedicated to IGBT, replacing float-zone silicon)

MCZ low-oxygen Czochralski crystals yield polished wafers with an oxygen content of ≤ 5 ppma, replacing float-zone (FZ) silicon and reducing the impact of thermal donors and bulk micro-defects on IGBTs. Radial oxygen-distribution control improves low CP yield and excessive VR at the IGBT edge region.

Customer benefit: in volume production at Chinese customers for automotive-grade products; product series at 90 / 60 / 45 / 30 Ω·cm.

③ Vacancy-type COP-free crystal growth

Growth-process control produces COP-free crystals, eliminating GOI failures caused by very small COPs.

Customer benefit: for gate-oxide-integrity-sensitive devices such as BCD, reduces GOI failure risk.

④ BMD internal gettering and full-process metal control

Combines BMD density control with full-process metal control to deliver low-metal-content wafers.

Customer benefit: reduces leakage and GOI failure risk.

⑤ Ultra-high-resistivity crystal pulling (dedicated to RF MEMS)

Uses boron as the dopant to achieve ultra-high-resistivity crystals above 10000 Ω·cm.

Customer benefit: gives precision sensing and RF devices a substrate with low signal loss, high thermal stability and high insulation.

⑥ Surface poly micro-polishing / Trap-Rich

Pairs a high-resistivity silicon substrate with a Trap-Rich (poly) layer. On standard high-resistivity silicon, fixed oxide charges at the Si/SiO2 interface attract free carriers and create parasitic surface conduction (PSC), which lowers the effective substrate resistivity. The Trap-Rich layer introduces deep-level traps at the interface to capture carriers and restore high-resistivity behaviour. Poly-layer micro-polishing removes 0.4 ± 0.1 μm of material, leaving a roughness of < 0.7 nm.

Customer benefit: maintains effective resistivity on high-resistivity substrates, significantly improves Qp, and meets device surface-roughness requirements.

⑦ MEMS warp/bow control

Controls wafer-parameter uniformity to strengthen stress resistance and reduce deformation after high-temperature device processing.

Customer benefit: reduces backpressure alarms caused by excessive warp after complex MEMS film-layer processes.

⑧ (110) crystal

Advantage: <110> offers significantly higher hole mobility than <100> — with strain engineering, PMOS hole mobility improves by 162% — and compressive-stress transfer efficiency improves by 40%.

Availability: QL has full-flow (110) wafer processing in place (crystal growth → slicing → lapping → polishing → cleaning → epitaxy), with samples available on request and all parameters customizable.

Applications

  • Power devices: MOSFET, FRD, SBD, TMBS, TVS, IGBT, etc.
  • Digital / analog ICs: BCD, PMIC, HVIC, Logic, MCU, etc.
  • Memory devices: DRAM, NOR Flash, NAND, etc.
  • MEMS: pressure sensors, silicon microphones, silicon lenses, RF MEMS, etc.
  • Test wafers: IMP Rs, Particle, Film Monitor, etc.